? semiconductor components industries, llc, 2014 september, 2014 ? rev. 8 1 publication order number: mc74vhc373/d mc74vhc373 octal d-type latch with 3-state output the mc74vhc373 is an advanced high speed cmos octal latch with 3?state output fabricated with silicon gate cmos technology. it achieves high speed operation similar to equivalent bipolar schottky ttl while maintaining cmos low power dissipation. this 8?bit d?type latch is controlled by a latch enable input and an output enable input. when the output enable input is high, the eight outputs are in a high impedance state. the internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. the inputs tolerate voltages up to 7.0 v, allowing the interface of 5.0 v systems to 3.0 v systems. features ? high speed: t pd = 5.0 ns (typ) at v cc = 5.0 v ? low power dissipation: i cc = 4.0 a (max) at t a = 25 c ? high noise immunity: v nih = v nil = 28% v cc ? power down protection provided on inputs ? balanced propagation delays ? designed for 2.0 v to 5.5 v operating range ? low noise: v olp = 0.9 v (max) ? pin and function compatible with other standard logic families ? latchup performance exceeds 300 ma ? esd performance: hbm > 2000 v; machine model > 200 v ? chip complexity: 186 fets or 46.5 equivalent gates ? these devices are pb?free and are rohs compliant pin assignment q2 d1 d0 q0 oe gnd q3 d3 d2 q1 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 q6 d6 d7 q7 v cc le q4 d4 d5 q5 http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ordering information marking diagram soic?20 dw suffix case 751d vhc373 awlyywwg 1 20 1 20 vhc373 = specific device code a = assembly location wl, l = wafer lot y = year ww, w = work week g or = pb?free package (note: microdot may be in either location)
mc74vhc373 http://onsemi.com 2 figure 1. logic diagram data inputs d0 d1 d2 d3 d4 d5 d6 d7 18 17 14 13 8 7 4 3 1 oe 19 q0 q1 q2 q3 q4 q5 q6 q7 16 15 12 9 6 5 2 noninverting outputs 11 le oe le q l l l h h h l x h l no change z inputs output function table d h l x x maximum ratings symbol parameter value unit v cc dc supply voltage ? 0.5 to + 7.0 v v in dc input voltage ? 0.5 to + 7.0 v v out dc output voltage ? 0.5 to v cc + 0.5 v i ik input diode current ? 20 ma i ok output diode current 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air, soic package? 500 mw t stg storage temperature ? 65 to + 150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ?derating ? soic package: ? 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage 2.0 5.5 v v in dc input voltage 0 5.5 v v out dc output voltage 0 v cc v t a operating temperature ? 40 + 85 c t r , t f input rise and fall time v cc = 3.3 v v cc = 5.0 v 0 0 100 20 ns/v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74vhc373 http://onsemi.com 3 dc electrical characteristics symbol parameter test conditions v cc v t a = 25 c t a = ? 40 to 85 c uni t min typ max min max v ih minimum high?level input voltage 2.0 3.0 to 5.5 1.50 v cc x 0.7 1.50 v cc x 0.7 v v il maximum low?level input voltage 2.0 3.0 to 5.5 0.50 v cc x 0.3 0.50 v cc x 0.3 v v oh minimum high?level output voltage v in = v ih or v il i oh = ? 50 a 2.0 3.0 4.5 1.9 2.9 4.4 2.0 3.0 4.5 1.9 2.9 4.4 v v in = v ih or v il i oh = ? 4 ma i oh = ? 8 ma 3.0 4.5 2.58 3.94 2.48 3.80 v ol maximum low?level output voltage v in = v ih or v il i ol = 50 a 2.0 3.0 4.5 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il i ol = 4 ma i ol = 8 ma 3.0 4.5 0.36 0.36 0.44 0.44 i in maximum input leakage current v in = 5.5 v or gnd 0 to 5.5 0.1 1.0 a i oz maximum three?state leakage current v in = v il or v ih v out = v cc or gnd 5.5 0.25 2.5 a i cc maximum quiescent supply current v in = v cc or gnd 5.5 4.0 40.0 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. ac electrical characteristics (input t r = t f = 3.0ns) symbol parameter test conditions t a = 25 c t a = ? 40 to 85 c uni t min typ max min max t plh , t phl maximum propagation delay, d to q v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf 7.3 9.8 11.4 14.9 1.0 1.0 13.5 17.0 ns v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf 4.9 6.4 7.2 9.2 1.0 1.0 8.5 10.5 t plh , t phl maximum propagation delay, le to q v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf 7.0 9.5 11.0 14.5 1.0 1.0 13.0 16.5 ns v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf 5.0 6.5 7.2 9.2 1.0 1.0 8.5 10.5 t pzl , t pzh output enable time, oe to q v cc = 3.3 0.3 v c l = 15 pf r l = 1 k c l = 50 pf 7.3 9.8 11.4 14.9 1.0 1.0 13.5 17.0 ns v cc = 5.0 0.5 v c l = 15 pf r l = 1 k c l = 50 pf 5.5 7.0 8.1 10.1 1.0 1.0 9.5 11.5 t plz , t phz output disable time, oe to q v cc = 3.3 0.3 v c l = 50 pf r l = 1 k 9.5 13.2 1.0 15.0 ns v cc = 5.0 0.5v c l = 50 pf r l = 1 k 6.5 9.2 1.0 10.5 t oslh , t oshl output to output skew v cc = 3.3 0.3 v c l = 50 pf (note 1) 1.5 1.5 ns v cc = 5.5 0.5 v c l = 50 pf (note 1) 1.0 1.0 ns
mc74vhc373 http://onsemi.com 4 ac electrical characteristics (input t r = t f = 3.0ns) symbol unit t a = ? 40 to 85 c t a = 25 c test conditions parameter symbol unit max min max typ min test conditions parameter c in maximum input capacitance 4 10 10 pf c out maximum three?state output capacitance (output in high?impedance state) 6 pf c pd power dissipation capacitance (note 2) typical @ 25 c, v cc = 5.0 v pf 27 1. parameter guaranteed by design. t oslh = |t plhm ? t plhn |, t oshl = |t phlm ? t phln |. 2. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc / 8 (per latch). c pd is used to determine the no?load dynamic power consumption; p d = c pd v cc 2 f in + i cc v cc . noise characteristics (input t r = t f = 3.0ns, c l = 50 pf, v cc = 5.0v) symbol parameter t a = 25 c unit typ max v olp quiet output maximum dynamic v ol 0.6 0.9 v v olv quiet output minimum dynamic v ol ? 0.6 ? 0.9 v v ihd minimum high level dynamic input voltage 3.5 v v ild maximum low level dynamic input voltage 1.5 v timing requirements (input t r = t f = 3.0 ns) symbol parameter test conditions t a = 25 c t a = ? 40 to 85 c unit typ limit limit t w(h) minimum pulse width, le v cc = 3.3 0.3 v v cc = 5.0 0.5 v 5.0 5.0 5.0 5.0 ns t su minimum setup time, d to le v cc = 3.3 0.3 v v cc = 5.0 0.5 v 4.0 4.0 4.0 4.0 ns t h minimum hold time, d to le v cc = 3.3 0.3 v v cc = 5.0 0.5 v 1.0 1.0 1.0 1.0 ns ordering information device package shipping ? mc74vhc373dwr2g soic?20 (pb?free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc74vhc373 http://onsemi.com 5 switching waveforms figure 2. figure 3. v cc gnd d q 50% 50% vcc t plh t phl v cc gnd 50% le t plh t phl q t w 50% vcc figure 4. figure 5. 50% 50% vcc 50% vcc q t pzl t plz t pzh t phz vol +0.3v vol -0.3v v cc gnd high impedance high impedance q oe 50% d le v cc v cc gnd gnd valid t h t su 50% test circuits *includes all probe and jig capacitance c l * test point device under test output figure 6. figure 7. *includes all probe and jig capacitance c l * test point device under test output connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . 1 k
mc74vhc373 http://onsemi.com 6 figure 8. expanded logic diagram d0 3 dq le 2 q0 11 1 d1 4 dq le 5 q1 d2 7 dq le 6 q2 d3 8 dq le 9 q3 d4 13 dq le 12 q4 d5 14 dq le 15 q5 d6 17 dq le 16 q6 d7 18 dq le 19 q7 le oe figure 9. input equivalent circuit input
mc74vhc373 http://onsemi.com 7 package dimensions soic?20 dw suffix case 751d?05 issue g 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74vhc373/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
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